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coreboot/src/southbridge
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Vadim Bendebury 459b7777fe add new LPC controller device ID value 
This adds the PCI device id of the LPC controller identifying the
QPRJ/QS stepping of the Panther Point southbridge.

Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/968
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01 20:03:31 +02:00
..
amd Do not produce temp s3.rom if the board doesn't need it. 2012-04-19 08:46:14 +02:00
broadcom Get rid of the old romstage-as-bootblock ROM layout 2011-10-28 22:17:36 +02:00
intel add new LPC controller device ID value 2012-05-01 20:03:31 +02:00
nvidia nvidia/mcp55: Move HAVE_HARD_RESET to southbridge 2012-02-17 22:41:58 +01:00
rdc Add support for RDC R8610 Southbridge 2012-03-27 18:39:05 +02:00
ricoh add functions to set Subsystem Vendor/Device to rl5c746 2011-02-28 18:09:58 +00:00
sis sis/sis966: Move HAVE_HARD_RESET to southbridge 2012-02-17 22:41:46 +01:00
ti remove trailing whitespace 2011-11-01 19:07:45 +01:00
via VIA southbridge K8T890: Apply un-written naming rules 2012-03-16 19:45:47 +01:00
Kconfig Add support for RDC R8610 Southbridge 2012-03-27 18:39:05 +02:00
Makefile.inc Add support for RDC R8610 Southbridge 2012-03-27 18:39:05 +02:00