Angel Pons 7adfe80469 nb/intel/haswell: Replace DMIBAR64 and EPBAR64 ... While 64-bit writes seem to work properly, there could be unknown side-effects in some cases, e.g. when running in long mode. Since reference code uses two 32-bit writes, follow suit. Change-Id: I48ed3d94c7865b3a3cce52108e99cf1656b57fc2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51855 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-03-28 18:00:49 +00:00
..
acpi	ACPI: Add SATC structure for DMAR table	2021-03-28 16:03:21 +00:00
arch
commonlib	cbfs: Move stage header into a CBFS attribute	2021-03-17 08:10:00 +00:00
console
cpu	cpu/x86/smm: Fix SMM start address passing	2021-03-24 15:36:36 +00:00
device	device/azalia_device.c: Program beep verbs	2021-03-24 07:55:15 +00:00
drivers	drivers/analogix: Increase the clock tolerance from 0.1% to 2%	2021-03-27 10:02:18 +00:00
ec
include	ACPI: Add SATC structure for DMAR table	2021-03-28 16:03:21 +00:00
lib	spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()	2021-03-17 08:10:35 +00:00
mainboard	mb/google/dedede/var/boten: Fix DPTF passive and critical policies	2021-03-28 16:08:17 +00:00
northbridge	nb/intel/haswell: Replace DMIBAR64 and EPBAR64	2021-03-28 18:00:49 +00:00
security	security/intel/cbnt: Generate KM from Kconfig symbols	2021-03-28 15:56:49 +00:00
soc	soc/intel/alderlake: add processor power limits control support	2021-03-28 16:08:02 +00:00
southbridge	nb/intel/haswell: Move USB config API into Lynx Point	2021-03-25 07:51:50 +00:00
superio	acpi/acpigen.h: Add more intuitive AML package closing functions	2021-03-22 11:21:55 +00:00
vendorcode	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02	2021-03-23 20:23:05 +00:00
Kconfig