coreboot/src/soc
Patrick Rudolph 7a66ffb34a soc/intel/common/block/acpi: Fix get_cores_per_package
Current implementation uses CPUID 0Bh function that returns the number
of logical cores of requested level. The problem with this approach is
that this value doesn't change when HyperThreading is disabled (it's in
the Intel docs), so it breaks generate_cpu_entries() because `numcpus`
ends up being zero due to integer division truncation.

- Use MSR 0x35 instead, which returns the correct number of logical
  processors with and without HT.

- Use cpu_read_topology() to gather the required information

Tested on Prodrive Hermes, the ACPI code is now generated even with
HyperThreading disabled.

Change-Id: Id9b985a07cd3f99a823622f766c80ff240ac1188
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-22 22:22:21 +00:00
..
amd soc/amd/common/psp: Remove files from bootblock 2020-12-22 17:07:07 +00:00
cavium cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
example x86: Add a minimal example SoC along with a board 2020-10-30 21:34:18 +00:00
intel soc/intel/common/block/acpi: Fix get_cores_per_package 2020-12-22 22:22:21 +00:00
mediatek soc/mediatek/mt8192: Do dramc software impedance calibration 2020-12-22 03:00:56 +00:00
nvidia drivers: Replace set_vbe_mode_info_valid 2020-12-17 06:21:56 +00:00
qualcomm cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
rockchip drivers: Replace set_vbe_mode_info_valid 2020-12-17 06:21:56 +00:00
samsung cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
sifive cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ti cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ucb soc/ucb/riscv: Add chip_operations stub 2020-05-28 09:30:35 +00:00