coreboot/src/soc
Duncan Laurie 791d0580b8 broadwell: Fix SATA Gen3 DTLE configuration registers
The port0 and port1 registers were swapped, which meant it did
not work to apply the DTLE settings to the correct SATA port.

This was tested on an unreleased mainboard but is verified with
the documentation to be the correct register addresses now.

Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12793
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27 17:42:58 +01:00
..
broadcom/cygnus arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
imgtec/pistachio imgtec/pistachio: DDR2, DDR3: DLL reset set 2015-12-21 02:06:12 +01:00
intel broadwell: Fix SATA Gen3 DTLE configuration registers 2015-12-27 17:42:58 +01:00
marvell/bg4cd arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
mediatek/mt8173 soc/mediatek/mt8173: SPI_ATOMIC_SEQUENCING depends on SPI_FLASH 2015-12-10 16:37:05 +01:00
nvidia arm64: tegra132: tegra210: Remove old arm64/stage_entry.S 2015-11-17 21:31:20 +01:00
qualcomm/ipq806x cbfs_spi: enable CBFS access in early romstage 2015-12-03 14:17:04 +01:00
rockchip/rk3288 google/veyron*: Pulse the i2c clock once if sda was low 2015-11-18 16:29:16 +01:00
samsung soc/samsung/exynos5250: Implement hard_reset() 2015-12-16 00:41:03 +01:00
ucb/riscv tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00