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coreboot/src/soc
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Lijian Zhao 79152f3c81 soc/intel/cannonlake: Add options for pcie ltr 
FSP can support enable/disable Pci express LTR (Latency Tolerance
Reporting) mechanism through upd interface. Include that into coreboot
side.

BUG=N/A
TEST=N/A

Change-Id: I69b423afa4f81a2d58375734bba07792e08931d5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29642
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-17 07:25:54 +00:00
..
amd {soc,sb}/amd: Remove unused SOUTHBRIDGE_AMD_*_SKIP_ISA_DMA_INIT 2018-11-16 14:25:10 +00:00
broadcom src: Remove unneeded include <cbfs.h> 2018-11-16 10:26:32 +00:00
cavium src: Get rid of duplicated includes 2018-11-16 09:50:03 +00:00
imgtec src: Remove unneeded include <console/console.h> 2018-11-16 09:50:29 +00:00
intel soc/intel/cannonlake: Add options for pcie ltr 2018-11-17 07:25:54 +00:00
mediatek src: Remove unneeded include <cbfs.h> 2018-11-16 10:26:32 +00:00
nvidia src: Remove unneeded include <cbmem.h> 2018-11-16 10:56:47 +00:00
qualcomm soc/qualcomm/ipq{40xx,806x}/Kconfig: Remove unused MBN_ENCAPSULATION 2018-11-16 09:57:08 +00:00
rockchip src: Remove unneeded include <cbmem.h> 2018-11-16 10:56:47 +00:00
samsung src: Remove unneeded include <cbmem.h> 2018-11-16 10:56:47 +00:00
sifive riscv: add support smp_pause / smp_resume 2018-11-05 09:03:40 +00:00
ucb riscv: add support smp_pause / smp_resume 2018-11-05 09:03:40 +00:00