coreboot/src/cpu
Nico Huber 68ddc60123 cpu/via/c7: Compress ramstage with LZ4 by default
It's a slow CPU.

Change-Id: I0bf75f410c1d9134f05a2d11b8d011499a7cf794
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82772
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-21 09:26:17 +00:00
..
amd treewide: Remove unused CHIPs 2024-02-20 11:01:36 +00:00
armltd arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
intel tree: Include static.h for remaining devicetree usages 2024-11-10 19:12:22 +00:00
power9 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-power8 include/device/device.h: Remove CHIP_NAME() macro 2024-01-31 09:51:58 +00:00
qemu-x86 mb/emulation/qemu: Configure TSEG size 2024-06-21 15:52:24 +00:00
via cpu/via/c7: Compress ramstage with LZ4 by default 2024-11-21 09:26:17 +00:00
x86 soc/intel/xeon_sp: Reserve PRMRR 2024-11-14 14:29:23 +00:00
Kconfig arch to cpu: Add SPDX license headers to Kconfig files 2024-02-18 01:58:52 +00:00
Makefile.mk via: Start template for VIA C7 w/ CX700 northbridge 2024-11-11 09:16:55 +00:00