coreboot/src/include/cpu/intel
Kyösti Mälkki f72cc4f746 UPSTREAM: intel post-car: Separate files for setup_stack_and_mtrrs()
Have a common romstage.c file to prepare CAR stack guards.

MTRR setup around cbmem_top() is somewhat northbridge specific,
place stubs under northbridge for platrform that will move
to RELOCATABLE_RAMSTAGE.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15762
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
Reviewed-on: https://chromium-review.googlesource.com/411427
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14 19:58:38 -08:00
..
hyperthreading.h
l2_cache.h
microcode.h
romstage.h UPSTREAM: intel post-car: Separate files for setup_stack_and_mtrrs() 2016-11-14 19:58:38 -08:00
speedstep.h UPSTREAM: cpu/intel: Add MSR to support enabling turbo frequency 2016-11-10 18:31:24 -08:00
turbo.h UPSTREAM: soc/intel/apollolake: Disable Monitor and Mwait feature 2016-11-04 04:53:33 -07:00