coreboot/src/northbridge
Aaron Durbin 76c3700f02 haswell: Add initial support for Haswell platforms
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore,
the southbridge support is included as well. The basis for this code is
the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires
more attention, but this is a good starting point.

This code partially gets up through the romstage just before training
memory on a Haswell reference board.

Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2616
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 01:44:40 +01:00
..
amd AMD Fam14: Add SPD read functions to wrapper code 2013-03-07 18:29:23 +01:00
intel haswell: Add initial support for Haswell platforms 2013-03-14 01:44:40 +01:00
rdc GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
via GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
Kconfig Add the support for RDC R8610 Northbridge 2012-03-27 18:37:57 +02:00
Makefile.inc Add the support for RDC R8610 Northbridge 2012-03-27 18:37:57 +02:00