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coreboot/src/cpu/intel
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Edward O'Callaghan 76a1437dbe cpu/intel/model_2065x/model_2065x_init.c: Remove dead code 
Unused array is dead code. Spotted by Clang build.

Change-Id: I11397716b39de08f1226413019e3beeeeaac6149
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6131
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-07-30 02:05:00 +02:00
..
car Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
ep80579 Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
fit x86 intel: Add Firmware Interface Table support 2013-03-17 22:53:51 +01:00
fsp_model_206ax cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro IS_ENABLED() 2014-07-23 10:18:50 +02:00
haswell intel/haswell: add vmx support w/Kconfig option 2014-07-10 16:46:41 +02:00
hyperthreading cpu: Trivial - drop trailing blank lines at EOF 2014-07-08 13:52:43 +02:00
microcode intel: fix microcode compilation failure in bootblock 2014-01-28 19:54:29 +01:00
model_6bx cpu: Trivial - drop trailing blank lines at EOF 2014-07-08 13:52:43 +02:00
model_6dx Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_6ex cpu: Trivial - drop trailing blank lines at EOF 2014-07-08 13:52:43 +02:00
model_6fx cpu: Trivial - drop trailing blank lines at EOF 2014-07-08 13:52:43 +02:00
model_6xx Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_65x Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_67x Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_68x cpu: Trivial - drop trailing blank lines at EOF 2014-07-08 13:52:43 +02:00
model_69x Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_106cx cpu: Trivial - drop trailing blank lines at EOF 2014-07-08 13:52:43 +02:00
model_206ax cpu: Trivial - drop trailing blank lines at EOF 2014-07-08 13:52:43 +02:00
model_1067x Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_2065x cpu/intel/model_2065x/model_2065x_init.c: Remove dead code 2014-07-30 02:05:00 +02:00
model_f0x Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_f1x Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_f2x Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_f3x Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
model_f4x Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
slot_1 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
slot_2 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_441 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_BGA956 Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
socket_FC_PGA370 Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
socket_LGA771 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
socket_LGA775 Fix socket LGA775 2013-03-07 00:46:32 +01:00
socket_mFCBGA479 Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
socket_mFCPGA478 Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
socket_mPGA478 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_mPGA479M Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
socket_mPGA603 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_mPGA604 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_PGA370 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF 2014-07-17 02:20:12 +02:00
socket_rPGA988B Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
socket_rPGA989 Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
speedstep sconfig: rename lapic_cluster -> cpu_cluster 2013-02-14 07:07:20 +01:00
thermal_monitoring
turbo cpu/intel: allow non-packaged scoped turbo setting 2014-01-30 06:10:26 +01:00
Kconfig cpu/intel: Add CPU socket rPGA988B 2014-05-13 21:58:16 +02:00
Makefile.inc sandy/ivybridge: Native raminit. 2014-07-29 00:52:28 +02:00