Aaron Durbin 746e598d07 soc/amd/common: add single function ACPI PM1 GPE helpers ... The existing code in common/block/acpi is mixing multiple operations: saving things to cbmem in common code but then soc code uses that information, reliant upon soc-specific struct soc_power_reg object, and only saving/snapshotting ACPI registers very deep in ramstage. To unwind the above provide some functions that are more targeted: - Add struct acpi_pm_gpe_state object - Add acpi_fill_pm_gpe_state() - Add acpi_pm_gpe_add_events_print_events() - Add acpi_clear_pm_gpe_status() BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia7afed2861343802b3c78728784f7cfaf6f53f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2020-08-17 17:39:54 +00:00
..
acpi	src/acpi: Add missing <{stdbool,stdint}.h>	2020-07-29 09:37:10 +00:00
arch	arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram	2020-08-17 06:22:41 +00:00
commonlib
console
cpu	cpu/Makefile.inc: Clean up non-existing directory inclusion	2020-08-17 06:24:23 +00:00
device	{sb/intel/*/azalia.c,device/azalia_device.c}: Reduce differences	2020-08-17 06:58:45 +00:00
drivers	src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers	2020-08-17 07:00:37 +00:00
ec	ec/google/chromeec: Add helper to request AP reset	2020-08-14 08:35:15 +00:00
include	soc/intel/common: Move common HDA registers to <device/azalia_device.h>	2020-08-17 06:44:04 +00:00
lib	lib/imd_cbmem.c: Add a helper function to indicate that cbmem is ready	2020-08-17 06:22:58 +00:00
mainboard	mb/google/volteer: Make devicetree default as Aux Orientation retimer controlled	2020-08-17 07:11:02 +00:00
northbridge	nb/amd/agesa: read 256 bytes to SPD buffer instead of 128	2020-08-17 07:13:05 +00:00
security	security/vboot/Makefile.inc: Update regions-for-file function	2020-08-13 05:43:53 +00:00
soc	soc/amd/common: add single function ACPI PM1 GPE helpers	2020-08-17 17:39:54 +00:00
southbridge	src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers	2020-08-17 07:00:37 +00:00
superio	superio/ite/it8728f: Correct Kconfig selections	2020-08-14 00:51:37 +00:00
vendorcode	vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable	2020-08-17 07:14:03 +00:00
Kconfig