Zheng Bao 3ea3fbe4f2 soc/amd: Add DBG2 ACPI table ... Dump the DBG2 table on Linux console. $> acpidump -s ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 **) $> acpidump > acpidump.bin $> acpixtract -a acpidump.bin $> iasl -d dbg2.dat $> cat dbg2.dsl /* * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000054 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20220331 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0028 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0002 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0012 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 006612] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 00000100 [052h 0082 2] Namepath : "." Raw Table Data: Length 84 (0x54) 00: 44 42 47 32 54 00 00 00 00 FA 43 4F 52 45 76 34 // DBG2T.....COREv4 10: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 20: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(.. 30: 02 00 26 00 00 00 00 00 00 80 12 00 00 00 16 00 // ..&............. 40: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "............... 50: 00 00 2E 00 // .... BUG=b:303689867 Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79174 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2023-12-02 17:51:42 +00:00
..
acpi	soc/amd: Add DBG2 ACPI table	2023-12-02 17:51:42 +00:00
arch	arch/x86/Makefile.inc: Do not pass CPPFLAGS to linker	2023-11-29 00:33:13 +00:00
commonlib	Allow to build romstage sources inside the bootblock	2023-11-09 13:20:18 +00:00
console	Allow to build romstage sources inside the bootblock	2023-11-09 13:20:18 +00:00
cpu	nb/intel/sandybridge: Use SA devid to identify PC type	2023-11-20 14:58:31 +00:00
device	device/Kconfig: rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT	2023-11-10 15:27:58 +00:00
drivers	drivers: spi_flash: Add space before colon to fix coding style	2023-11-16 11:59:20 +00:00
ec	ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h	2023-11-16 23:08:06 +00:00
include	soc/amd: Add DBG2 ACPI table	2023-12-02 17:51:42 +00:00
lib	lib/device_tree.c: Fix print_property	2023-11-16 12:01:40 +00:00
mainboard	mb/google/nissa/var/anraggar: Trim GPIO comments	2023-12-01 16:37:05 +00:00
northbridge	nb/amd/pi/00730F01: drop leftover family10_northbridge PCI driver	2023-12-01 00:05:57 +00:00
sbom	sbom/Makefile.inc: Change GOPATH	2023-11-20 14:32:54 +00:00
security	vboot: Add catchall recovery reason for unspecified phase 4 errors	2023-11-22 01:50:47 +00:00
soc	soc/amd: Add DBG2 ACPI table	2023-12-02 17:51:42 +00:00
southbridge	sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree	2023-11-18 16:36:46 +00:00
superio	superio/smsc: Add support for the SCH555x series	2023-12-01 17:40:11 +00:00
vendorcode	vendorcode/amd/opensil: Implement cbmem_top_chipset	2023-11-30 15:16:47 +00:00
Kconfig	Allow to build romstage sources inside the bootblock	2023-11-09 13:20:18 +00:00