733febf874
When doing long transcations on an I2C bus at standard speed we saw that long transactions could go over the 4ms limit while waiting for it to complete on the bus. Increase this so we can use standard speed for testing and debug in firmware. (as there is no way to force standard speed in the kernel) BUG=chrome-os-partner:58666 BRANCH=None TEST=boot eve board with cr50 TPM and I2C bus at 100khz Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17213 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f Reviewed-on: https://chromium-review.googlesource.com/408973 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
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