6cc5e52ec6
Some SOCs (like pistachio, for instance) provide an 8250 compatible
UART, which has the same register layout, but mapped to a bus of a
different width.
Instead of adding a new driver for these controllers, it is better to
have coreboot report UART register width to libpayload, and have it
adjust the offsets accordingly when accessing the UART.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the rest of the patches integrated depthcharge console messages
show up when running on the FPGA board
Change-Id: I05891a9471a5369d3bfafe90cd0c9b0a7e5a667e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42
Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240027
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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|---|---|---|
| .. | ||
| arm/arch | ||
| arm64/arch | ||
| arpa | ||
| mips/arch | ||
| pci | ||
| storage | ||
| sys | ||
| usb | ||
| x86/arch | ||
| assert.h | ||
| cbfs.h | ||
| cbfs_core.h | ||
| cbfs_ram.h | ||
| coreboot_tables.h | ||
| ctype.h | ||
| die.h | ||
| endian.h | ||
| errno.h | ||
| exception.h | ||
| gdb.h | ||
| getopt.h | ||
| inttypes.h | ||
| ipchksum.h | ||
| kconfig.h | ||
| keycodes.h | ||
| lar.h | ||
| libpayload.h | ||
| limits.h | ||
| lzma.h | ||
| malloc.h | ||
| multiboot_tables.h | ||
| panel.h | ||
| pci.h | ||
| queue.h | ||
| stdarg.h | ||
| stddef.h | ||
| stdint.h | ||
| stdio.h | ||
| stdlib.h | ||
| string.h | ||
| strings.h | ||
| swab.h | ||
| sysinfo.h | ||
| term.h | ||
| unistd.h | ||
| video_console.h | ||