coreboot/src
York Yang 72e33a75cb intel/fsp_baytrail: Load APs microcode in baytrail_init_cpus
Load microcode to APs when performing baytrail_init_cpus. The updated
fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP
will not handle the microcode load.

Change-Id: I7b7c0f43da0d149048ae5a8fd547828f42de04fd
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/12095
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16 17:43:18 +01:00
..
acpi tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
arch cpu/amd: Add CC6 support 2015-11-11 18:45:14 +01:00
commonlib commonlib: Remove unused static function. 2015-11-09 12:26:31 +01:00
console arm64: remove secmon 2015-11-07 03:28:06 +01:00
cpu intel/fsp_model_406dx: Load APs microcode in model_406dx_init 2015-11-16 17:41:00 +01:00
device tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
drivers intel/fsp1_0: Use dummy microcode when calling FSP TempRamInit 2015-11-16 17:42:36 +01:00
ec tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
include cpu/amd: Add CC6 support 2015-11-11 18:45:14 +01:00
lib arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
mainboard newisys: Remove mainboard directory and Kconfig files 2015-11-13 01:30:32 +01:00
northbridge nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots 2015-11-16 17:31:48 +01:00
soc intel/fsp_baytrail: Load APs microcode in baytrail_init_cpus 2015-11-16 17:43:18 +01:00
southbridge src/southbridge/amd/sr5650: Always configure lane director on startup 2015-11-15 02:46:57 +01:00
superio Drop SuperIO fintek/f71889 2015-11-10 20:16:49 +01:00
vendorcode AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1 2015-11-12 22:42:04 +01:00
Kconfig arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00