coreboot/src/soc/intel
Aaron Durbin 71e0ac858e skylake: provide clarification for FADT gpe0_blk_len
Instead of using a hard-coded value leverage the existing
definitions to perform GPE0 block length calculations. There
are 4 pairs of 32-bit status/enable registers.

BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291932
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11205
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:20:57 +02:00
..
baytrail x86: Drop -Wa,--divide 2015-07-07 18:30:55 +02:00
braswell intel/common: fix stage_cache_external_region() 2015-08-14 15:19:31 +02:00
broadwell azalia: fix up and clean up shrinkage of boilerplate code 2015-07-14 13:40:07 +02:00
common intel/common: fix stage_cache_external_region() 2015-08-14 15:19:31 +02:00
fsp_baytrail intel/fsp_baytrail: Support Baytrail FSP Gold4 release 2015-07-21 22:32:23 +02:00
skylake skylake: provide clarification for FADT gpe0_blk_len 2015-08-14 15:20:57 +02:00