Subrata Banik 71a5138807 soc/intel/cannonlake: Reserve PMC IO resources ... PMC controller gets hidden during FSP Silicon initialization using sideband interface on CNP-PCH. Hence unable to reserve PMC IO resources during PCI enumeration process. This causes hang issue on non-chrome platform with CNP-PCH due to ABASE corruption. This patch ensures PMC IO resource (ABASE) is getting reserved (IO address 0x1800-0x1900) and ACPI base is not overwritten by other devices. TEST=ABASE range is reserved along with LPC IO range during PCI enumeration. PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20 Change-Id: I1fbc4339ae11058fb3daedf4ffedda1904fa52ec Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-01-17 17:47:48 +00:00
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apollolake	soc/intel/common: Add option to pass SoC IO resource	2018-01-17 17:47:33 +00:00
baytrail	drivers/mrc_cache: move mrc_cache support to drivers	2017-12-17 18:29:41 +00:00
braswell	drivers/mrc_cache: move mrc_cache support to drivers	2017-12-17 18:29:41 +00:00
broadwell	drivers/mrc_cache: move mrc_cache support to drivers	2017-12-17 18:29:41 +00:00
cannonlake	soc/intel/cannonlake: Reserve PMC IO resources	2018-01-17 17:47:48 +00:00
common	soc/intel/common: Add option to pass SoC IO resource	2018-01-17 17:47:33 +00:00
denverton_ns	soc/intel/denverton_ns: Add Denverton-AD system agent id	2017-12-20 16:40:53 +00:00
fsp_baytrail	soc/intel/fsp_baytrail: remove nvm headers and code	2017-12-17 18:29:08 +00:00
fsp_broadwell_de	Constify struct cpu_device_id instances	2017-11-23 05:00:17 +00:00
quark	soc/intel/quark/spi: Correct conversion specifier	2017-11-03 15:22:06 +00:00
skylake	soc/intel/common: Add option to pass SoC IO resource	2018-01-17 17:47:33 +00:00
Kconfig	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00