coreboot/src/soc/intel/common
Aaron Durbin 9796f60c62 coreboot: move TS_END_ROMSTAGE to one spot
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
     timestamp table.

Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-24 16:12:44 +00:00
..
acpi intel/common: Add common code for filling out ACPI _SWS 2015-09-17 14:13:37 +00:00
acpi.h intel/common: Add common code for filling out ACPI _SWS 2015-09-17 14:13:37 +00:00
acpi_wake_source.c intel/common: Add common code for filling out ACPI _SWS 2015-09-17 14:13:37 +00:00
fsp_ramstage.c fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
gma.h Intel/common: Remove copyright address 2015-06-24 17:05:35 +02:00
hda_verb.c Intel Common SOC: Add romstage support 2015-06-24 17:05:06 +02:00
hda_verb.h Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
Kconfig intel/common: Add common code for filling out ACPI _SWS 2015-09-17 14:13:37 +00:00
Makefile.inc intel/common: Add common code for filling out ACPI _SWS 2015-09-17 14:13:37 +00:00
memmap.h intel/common: fix stage_cache_external_region() 2015-08-14 15:19:31 +02:00
mrc_cache.c bootstate: remove need for #ifdef ENV_RAMSTAGE 2015-09-04 21:01:58 +00:00
mrc_cache.h Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
nvm.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
nvm.h Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
raminit.c fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
ramstage.h fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
reset.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
romstage.c coreboot: move TS_END_ROMSTAGE to one spot 2015-09-24 16:12:44 +00:00
romstage.h fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
stack.c Intel/common: Remove copyright address 2015-06-24 17:05:35 +02:00
stack.h Intel/common: Remove copyright address 2015-06-24 17:05:35 +02:00
stage_cache.c intel/common: fix stage_cache_external_region() 2015-08-14 15:19:31 +02:00
util.c Intel/common: Remove copyright address 2015-06-24 17:05:35 +02:00
util.h Intel/common: Remove copyright address 2015-06-24 17:05:35 +02:00
vbt.c fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00