coreboot/src/soc/intel
Shelley Chen 7129cbf2f1 soc/intel/icelake: Open ports 0x60,0x64 for keyboard controller
BUG=b:112110028
BRANCH=none
TEST=boot into recovery
     in ec console:
     kblog on
     (type on keyboard)
     kblog
     make sure buffer is not empty

Change-Id: I6525c2a46eef835dc64682466364a5b8fbb35226
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-31 02:18:54 +00:00
..
apollolake src: Add missing include <stdint.h> 2018-10-30 09:41:08 +00:00
baytrail src: Add missing include <stdint.h> 2018-10-30 09:41:08 +00:00
braswell src: Add missing include <stdint.h> 2018-10-30 09:41:08 +00:00
broadwell vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic 2018-10-24 09:07:43 +00:00
cannonlake src: Add missing include <stdint.h> 2018-10-30 09:41:08 +00:00
common src: Add missing include <stdint.h> 2018-10-30 09:41:08 +00:00
denverton_ns soc/intel: Consolidate FSP CAR setup and teardown code 2018-10-25 09:26:50 +00:00
fsp_baytrail src: Add missing include <stdint.h> 2018-10-30 09:41:08 +00:00
fsp_broadwell_de intel: Use CF9 reset (part 1) 2018-10-22 08:35:25 +00:00
icelake soc/intel/icelake: Open ports 0x60,0x64 for keyboard controller 2018-10-31 02:18:54 +00:00
quark intel: Use CF9 reset (part 2) 2018-10-22 08:35:32 +00:00
skylake soc/intel/*: Make FSP header path user configurable 2018-10-27 23:58:15 +00:00
Kconfig soc/intel/icelake: Do initial SoC commit 2018-10-26 11:20:54 +00:00