Raul E Rangel 6f1d35e72d soc/amd/picasso/bootblock: Clear BSS section ... We are currently relying on the assumption that the amdcompress tool will zero out the bss section. Instead of relying on this assumption, lets explicitly clear it. The implementation was copied from assembly_entry.S. BUG=b:147042464 TEST=Cold boot trembyle and also s3 resume trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb4f4cc6932dd4c3c92d4e7647569f9a0c69ea4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2020-06-22 11:51:56 +00:00
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amd	soc/amd/picasso/bootblock: Clear BSS section	2020-06-22 11:51:56 +00:00
cavium	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
intel	cpu/x86/smm: Define APM_CNT_NOOP_SMI	2020-06-22 11:44:45 +00:00
mediatek	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
nvidia	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
qualcomm	soc/qualcomm/sc7180/qupv3_config.c: Add missing includes	2020-06-22 11:49:34 +00:00
rockchip	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
samsung	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
sifive	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00