coreboot/src/soc/intel
Duncan Laurie 6f0e6fa6e1 skylake: Finalize SMM in coreboot
Once we lock down the SPI BAR we need to tell SMM to re-init its
SPI driver or it will be unable to write ELOG events via SMI.

This SMI is also sent at the end of depthcharge so there was just
a window where SMI events could get lost.

BUG=chrome-os-partner:50076
BRANCH=glados
TEST=enable DEBUG_SMI, boot to dev screen, press power button and
see elog events get added without without transaction errors.

Change-Id: I1f14717b5e7f29c158dde8fd308bdbfb67eba41a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 60ca24c760c70e2ebe5f3e68f95d3ffdba0fef9e
Original-Change-Id: I4e323249f00954e290a6a30f515e34632681bfdd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326861
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13697
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15 08:07:11 +01:00
..
apollolake soc/intel/apollolake: add assert for pad constraints 2016-02-13 01:16:27 +01:00
baytrail ACPI: Fix IASL Warning about unused method for GBUF check 2015-12-10 16:30:50 +01:00
braswell timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig 2016-02-12 21:54:52 +01:00
broadwell chromeos: Remove CONFIG_VBNV_SIZE variable 2016-02-09 13:19:48 +01:00
common soc/intel/common: Use SoC specific routine to read/write MTRRs 2016-02-02 19:00:35 +01:00
fsp_baytrail soc/fsp_baytrail: Add support for FSP MR 005 2016-02-10 02:45:56 +01:00
quark soc/intel/quark: Report CPU info 2016-02-10 03:12:18 +01:00
skylake skylake: Finalize SMM in coreboot 2016-02-15 08:07:11 +01:00