69451f17a1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia40678019b2a54deb246dbfbf33ec37a8c3839e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <delay.h>
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#include <spi_bitbang.h>
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#include <types.h>
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/* Set to 1 to dump all SPI transfers to the UART. */
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#define TRACE 0
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/*
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* In theory, this should work fine with 0 delay since the bus is fully clocked
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* by the master and the slave just needs to follow clock transitions whenever
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* they happen. We're not going to be "too fast" by bit-banging anyway. However,
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* if something doesn't work right, try increasing this value to slow it down.
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*/
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#define HALF_CLOCK_US 0
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int spi_bitbang_claim_bus(const struct spi_bitbang_ops *ops)
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{
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ops->set_cs(ops, 0);
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return 0;
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}
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void spi_bitbang_release_bus(const struct spi_bitbang_ops *ops)
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{
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ops->set_cs(ops, 1);
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}
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/* Implements a CPOL=0, CPH=0, MSB first 8-bit controller. */
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int spi_bitbang_xfer(const struct spi_bitbang_ops *ops, const void *dout,
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size_t bytes_out, void *din, size_t bytes_in)
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{
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if (TRACE) {
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if (bytes_in && bytes_out)
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printk(BIOS_SPEW, "!");
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else if (bytes_in)
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printk(BIOS_SPEW, "<");
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else if (bytes_out)
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printk(BIOS_SPEW, ">");
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}
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while (bytes_out || bytes_in) {
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int i;
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uint8_t in_byte = 0, out_byte = 0;
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if (bytes_out) {
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out_byte = *(const uint8_t *)dout++;
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bytes_out--;
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if (TRACE)
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printk(BIOS_SPEW, "%02x", out_byte);
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}
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for (i = 7; i >= 0; i--) {
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ops->set_mosi(ops, !!(out_byte & (1 << i)));
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if (HALF_CLOCK_US)
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udelay(HALF_CLOCK_US);
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ops->set_clk(ops, 1);
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in_byte |= !!ops->get_miso(ops) << i;
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if (HALF_CLOCK_US)
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udelay(HALF_CLOCK_US);
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ops->set_clk(ops, 0);
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}
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if (bytes_in) {
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*(uint8_t *)din++ = in_byte;
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bytes_in--;
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if (TRACE)
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printk(BIOS_SPEW, "%02x", in_byte);
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}
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}
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if (TRACE)
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printk(BIOS_SPEW, "\n");
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return 0;
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}
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