Michał Żygowski 6e61c5ec00 soc/intel/braswell: Generate microcode binaries from tree ... Automatically add microcode binaries from intel-microcode 3rdparty respository for Braswell processors using Makefile. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iec57e4d5cd63b9bccc869bf178053f1c99b81b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>		2020-03-07 17:51:32 +00:00
..
amd	soc/amd/picasso: Add PCI ID for Dali xHCI	2020-03-02 16:33:07 +00:00
cavium	soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>	2019-12-19 05:38:43 +00:00
intel	soc/intel/braswell: Generate microcode binaries from tree	2020-03-07 17:51:32 +00:00
mediatek	soc/mediatek/mt8183: Improve the DRAMC runtime config flow	2020-03-06 08:01:20 +00:00
nvidia	commonlib: Add commonlib/bsd	2020-01-28 06:36:13 +00:00
qualcomm	sc7180: clock: Fix QUP DFSR configuration for perf levels	2020-02-07 23:12:00 +00:00
rockchip	soc/rockchip: Fix typos	2020-02-24 13:04:02 +00:00
samsung	soc/{samsung,sifive}: Fix typos	2020-02-24 13:01:15 +00:00
sifive	soc/{samsung,sifive}: Fix typos	2020-02-24 13:01:15 +00:00
ucb	mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.	2019-12-06 15:09:48 +00:00