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coreboot/src/soc/qualcomm
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Venkateshwar S 03524780ff soc/qualcomm/x1p42100: Support loading QTEE FW config files 
This patch adds support to load the config files associated with
the QTEE firmware in X1P42100.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Ensure config files are loaded into the appropriate regions.

[INFO ]  CBFS: Found 'fallback/tzoem_cfg' @0x3ab3c0 size 0x3900
[DEBUG]  read SPI 0xfdb418 0x3900: 1200 us, 12160 KB/s, 97.280 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 14592 bytes, hash algo 2, HW acceleration
                forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd802a000 memsize 0x1d0 srcaddr
                0x9f80414c filesize 0xd2
[DEBUG]  Loading Segment: addr: 0xd802a000 memsz: 0x00000000000001d0
                filesz: 0x00000000000000d2
[DEBUG]  using LZMA
[SPEW ]  [ 0xd802a000, d802a1d0, 0xd802a1d0) <- 9f80414c
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd802f000 memsize 0x9000 srcaddr
                0x9f80421e filesize 0x37da
[DEBUG]  Loading Segment: addr: 0xd802f000 memsz: 0x0000000000009000
                filesz: 0x00000000000037da
[DEBUG]  using LZMA
[SPEW ]  [ 0xd802f000, d8038000, 0xd8038000) <- 9f80421e
[DEBUG]  Loading segment from ROM address 0x9f804130
[DEBUG]    Entry Point 0xd802f000
[SPEW ]  Loaded segments
[INFO ]  CBFS: Found 'fallback/tzqti_cfg' @0x3aed40 size 0x19c3
[DEBUG]  read SPI 0xfded98 0x19c3: 562 us, 11734 KB/s, 93.872 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 6595 bytes, hash algo 2, HW acceleration
                forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd803b000 memsize 0x1d0 srcaddr
                0x9f80414c filesize 0xd2
[DEBUG]  Loading Segment: addr: 0xd803b000 memsz: 0x00000000000001d0
                filesz: 0x00000000000000d2
[DEBUG]  using LZMA
[SPEW ]  [ 0xd803b000, d803b1d0, 0xd803b1d0) <- 9f80414c
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd8040000 memsize 0xe000 srcaddr
                0x9f80421e filesize 0x189d
[DEBUG]  Loading Segment: addr: 0xd8040000 memsz: 0x000000000000e000
                filesz: 0x000000000000189d
[DEBUG]  using LZMA
[SPEW ]  [ 0xd8040000, d804e000, 0xd804e000) <- 9f80421e
[DEBUG]  Loading segment from ROM address 0x9f804130
[DEBUG]    Entry Point 0xd8040000
[SPEW ]  Loaded segments
[INFO ]  CBFS: Found 'fallback/tzac_cfg' @0x3b0780 size 0x1f0d
[DEBUG]  read SPI 0xfe07d8 0x1f0d: 670 us, 11864 KB/s, 94.912 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 7949 bytes, hash algo 2, HW acceleration
                forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd8019000 memsize 0xb800 srcaddr
                0x9f804130 filesize 0x1ed5
[DEBUG]  Loading Segment: addr: 0xd8019000 memsz: 0x000000000000b800
                filesz: 0x0000000000001ed5
[DEBUG]  using LZMA
[SPEW ]  [ 0xd8019000, d8024800, 0xd8024800) <- 9f804130
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    Entry Point 0xd8019000
[SPEW ]  Loaded segments
[INFO ]  CBFS: Found 'fallback/hypac_cfg' @0x3b2700 size 0x11f2
[DEBUG]  read SPI 0xfe2758 0x11f2: 400 us, 11485 KB/s, 91.880 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
                supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 4594 bytes, hash algo 2, HW acceleration
                forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0xd8000000 memsize 0xc8f4 srcaddr
                0x9f804130 filesize 0x11ba
[DEBUG]  Loading Segment: addr: 0xd8000000 memsz: 0x000000000000c8f4
                filesz: 0x00000000000011ba
[DEBUG]  using LZMA
[SPEW ]  [ 0xd8000000, d800c8f4, 0xd800c8f4) <- 9f804130
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    Entry Point 0xd8000000
[SPEW ]  Loaded segments

Change-Id: If07840fca327e51c385dbe3f33b9f775bbee7654
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89550
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-10-22 17:08:35 +00:00
..
common soc/qualcomm/x1p42100: Add USB Type-C support 2025-10-12 04:40:18 +00:00
ipq40xx arch/arm: Add a few ARM targets as supported by CLANG 2024-08-23 10:40:01 +00:00
ipq806x arch/arm: Add a few ARM targets as supported by CLANG 2024-08-23 10:40:01 +00:00
qcs405 soc/qualcomm: Move common region macros to soc/memlayout.h 2025-08-17 01:10:35 +00:00
sc7180 soc/qualcomm: Move common region macros to soc/memlayout.h 2025-08-17 01:10:35 +00:00
sc7280 soc/qualcomm: Move common region macros to soc/memlayout.h 2025-08-17 01:10:35 +00:00
x1p42100 soc/qualcomm/x1p42100: Support loading QTEE FW config files 2025-10-22 17:08:35 +00:00