coreboot/src/soc/intel
Matt DeVillier b065e811bd soc/intel/cannonlake: Implement SoC sleep state array
Adapted from Alderlake implementation, modified as needed.
Device names missing from soc_acpi_name() were added as well.

TEST=build/boot Win11, Linux on google/hatch (akemi).

Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-31 15:06:27 +00:00
..
alderlake device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
apollolake soc/intel/apollolake: Select USE_LEGACY_8254_TIMER 2023-10-26 10:24:43 +00:00
baytrail x86: Add pre-memory stages CBFS cache scratchpad support 2023-10-20 14:32:44 +00:00
braswell x86: Add pre-memory stages CBFS cache scratchpad support 2023-10-20 14:32:44 +00:00
broadwell device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
cannonlake soc/intel/cannonlake: Implement SoC sleep state array 2023-10-31 15:06:27 +00:00
common soc/intel/cse: remove cbfs_unverified_area_map() API in cse_lite 2023-10-27 06:37:35 +00:00
denverton_ns device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
elkhartlake device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
jasperlake device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
meteorlake soc/intel/meteorlake: Expose In-Band ECC UPD config to mainboard 2023-10-28 21:02:09 +00:00
skylake device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
tigerlake soc/intel/tigerlake: Implement SoC sleep state array 2023-10-31 15:03:28 +00:00
xeon_sp soc/intel/xeon_sp/spr: Add SATA controllers 1 and 2 to devicetree 2023-10-13 13:51:50 +00:00
Makefile.inc soc/intel/Makefile.inc: Add comment where CONFIG_CSE_*_FILE are used 2023-09-22 15:48:08 +00:00