coreboot/src/arch
Ronald G. Minnich 0c2cba9dc0 UPSTREAM: riscv: enable counters via m[us]counteren
The user and supervisor counters could not be safely enabled
before as the register numbers were not finalized. Now that
everyone agrees, we can enable them. Until we are sure the
toolchains are caught up, we use the hardcode name with
the register names in comments. As soon as toolchains
settle down we'll do one more pass and convert to
the symbolic names.

Tested on lowrisc bitstream and SPIKE simulator.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17920
Tested-by: build bot (Jenkins)
Reviewed-by: Alex Bradbury <asb@lowrisc.org>
Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-by: Andrew Waterman <aswaterman@gmail.com>

Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6
Reviewed-on: https://chromium-review.googlesource.com/422950
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:13 -08:00
..
arm UPSTREAM: buildsystem: Drop explicit (k)config.h includes 2016-12-09 03:29:54 -08:00
arm64 UPSTREAM: buildsystem: Drop explicit (k)config.h includes 2016-12-09 03:29:54 -08:00
mips build system: remove CBFSTOOL_PRE1_OPTS 2016-05-03 11:40:49 +02:00
power8 UPSTREAM: region: Add writeat and eraseat support 2016-06-27 17:13:18 -07:00
riscv UPSTREAM: riscv: enable counters via m[us]counteren 2016-12-21 03:13:13 -08:00
x86 UPSTREAM: ACPI S3: Signal successful boot 2016-12-19 09:55:17 -08:00