coreboot/src
Angel Pons 6c49f40b6e haswell: Add Intel TXT support in romstage
Provide necessary romstage hooks to allow unblocking the memory with
SCLEAN. Note that this is slow, and took four minutes with 4 GiB of RAM.

Tested on Asrock B85M Pro4 with tboot. When Linux has tboot support
compiled in, booting as well as S3 suspend and resume are functional.
However, SINIT will TXT reset when the iGPU is enabled, and using a dGPU
will result in DMAR-related problems as soon as the IOMMU is enabled.

However, SCLEAN seems to hang sometimes. This may be because the AP
initialization that reference code does before SCLEAN is missing, but
the ACM is still able to unblock the memory. Considering that SCLEAN is
critical to recover an otherwise-bricked platform but is hardly ever
necessary, prefer having a partially-working solution over none at all.

Change-Id: I60beb7d79a30f460bbd5d94e4cba0244318c124e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-04 23:53:51 +00:00
..
acpi soc/intel/skl,acpi/acpigen: convert global CPPC package to local one 2020-11-04 09:40:21 +00:00
arch arch/x86/smbios: Populate SMBIOS type 7 with cache information 2020-10-26 06:54:04 +00:00
commonlib lib/libpayload: Replace strapping_ids with new board configuration entry 2020-10-30 15:25:28 +00:00
console console/init: Drop CONSOLE_LEVEL_CONST 2020-10-26 06:48:45 +00:00
cpu cpu/intel/haswell: Move smmrelocate.c MSR definitions to header 2020-11-03 19:12:01 +00:00
device azalia: Treat all negative return values as errors 2020-11-02 10:41:15 +00:00
drivers soc/intel/common: Create common Intel FSP reset code block 2020-11-02 10:43:40 +00:00
ec ec/purism/librem: Convert to ASL 2.0 syntax 2020-11-04 09:44:11 +00:00
include acpi/acpi.h: Update region spaces 2020-11-04 09:40:40 +00:00
lib lib/libpayload: Replace strapping_ids with new board configuration entry 2020-10-30 15:25:28 +00:00
mainboard mb/purism/librem_cnl: Set SaGv to FixedHigh 2020-11-04 23:47:09 +00:00
northbridge haswell: Add Intel TXT support in romstage 2020-11-04 23:53:51 +00:00
security haswell: Add Intel TXT support in romstage 2020-11-04 23:53:51 +00:00
soc soc/intel/broadwell: Merge device_nvs.asl into globalnvs.asl 2020-11-04 23:21:29 +00:00
southbridge sb/intel/lynxpoint/acpi/gpio.asl: Simplify constants 2020-11-04 23:22:04 +00:00
superio superio/nuvoton: Factor out equivalent Kconfig option 2020-10-19 07:06:20 +00:00
vendorcode vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 2020-11-02 04:43:39 +00:00
Kconfig soc/intel/xeon_sp: Move function debug macros 2020-10-29 16:44:19 +00:00