4cc9b6c78d
The EHCI hardware needs to be initialized only once during CAR stages. Some exception need to be made when a blob messes with the EHCI hardware. To achieve this add a fixed location in the car.ld linker script such that the ehci debug information can be shared across CAR stages. Currently this means only romstage and bootblock, but verstage can also be hooked up later on. Tested on google/peppy: Both the bootblock and the romstage properly output console. Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
125 lines
4.7 KiB
Text
125 lines
4.7 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Advanced Micro Devices, Inc.
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* Copyright (C) 2008-2010 coresystems GmbH
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* Copyright 2015 Google Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This file is included inside a SECTIONS block */
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. = CONFIG_DCACHE_RAM_BASE;
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.car.data . (NOLOAD) : {
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_car_region_start = . ;
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#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
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/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
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* aligned when using this option. */
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_pagetables = . ;
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. += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
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_epagetables = . ;
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#endif
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/* Vboot work buffer is completely volatile outside of verstage and
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* romstage. Appropriate code needs to handle the transition. */
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#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)
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VBOOT2_WORK(., 16K)
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#endif
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/* Stack for CAR stages. Since it persists across all stages that
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* use CAR it can be reused. The chipset/SoC is expected to provide
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* the stack size. */
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#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
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_car_stack_start = .;
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. += CONFIG_DCACHE_BSP_STACK_SIZE;
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_car_stack_end = .;
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#endif
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/* The pre-ram cbmem console as well as the timestamp region are fixed
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* in size. Therefore place them above the car global section so that
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* multiple stages (romstage and verstage) have a consistent
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* link address of these shared objects. */
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PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
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#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
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. = ALIGN(32);
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/* Page directory pointer table resides here. There are 4 8-byte entries
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* totalling 32 bytes that need to be 32-byte aligned. The reason the
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* pdpt are not colocated with the rest of the page tables is to reduce
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* fragmentation of the CAR space that persists across stages. */
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_pdpt = .;
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. += 32;
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_epdpt = .;
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#endif
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_car_relocatable_data_start = .;
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/* The timestamp implementation relies on this storage to be around
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* after migration. One of the fields indicates not to use it as the
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* backing store once cbmem comes online. Therefore, this data needs
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* to reside in the migrated area (between _car_relocatable_data_start
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* and _car_relocatable_data_end). */
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TIMESTAMP(., 0x200)
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#if IS_ENABLED(CONFIG_COMMONLIB_STORAGE)
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_car_drivers_storage_start = .;
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. += 256;
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_car_drivers_storage_end = .;
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#endif
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_car_ehci_dbg_info_start = .;
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. += 64;
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_car_ehci_dbg_info_end = .;
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/* _car_global_start and _car_global_end provide symbols to per-stage
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* variables that are not shared like the timestamp and the pre-ram
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* cbmem console. This is useful for clearing this area on a per-stage
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* basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
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_car_global_start = .;
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#if IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
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/* Allow global unitialized variables when CAR_GLOBALs are not used. */
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*(.bss)
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*(.bss.*)
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*(.sbss)
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*(.sbss.*)
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#else
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/* .car.global_data objects only around when
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* !CONFIG_NO_CAR_GLOBAL_MIGRATION is employed. */
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*(.car.global_data);
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#endif
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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_car_global_end = .;
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_car_relocatable_data_end = .;
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#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
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_car_stack_start = .;
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_car_stack_end = _car_region_end;
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#endif
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_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
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}
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/* Global variables are not allowed in romstage
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* This section is checked during stage creation to ensure
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* that there are no global variables present
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*/
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. = 0xffffff00;
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.illegal_globals . : {
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
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#if !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
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*(.bss)
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*(.bss.*)
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*(.sbss)
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*(.sbss.*)
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#else
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/* In case something sneaks through when it shouldn't. */
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*(.car.global_data);
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#endif
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}
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_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
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#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
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_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
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#endif
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#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
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_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
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#endif
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