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Raul E Rangel 6ba1fcac34 soc/amd/cezanne: Add SPI registers 
These are identical to picasso.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10 19:00:34 +00:00
..
acpi
arch acpi: Fix Coverity Scan report 2021-02-10 07:22:35 +00:00
commonlib
console
cpu
device device/azalia_device: Add mainboard hook to program codecs 2021-02-10 07:21:11 +00:00
drivers src: Remove unused <boot_device.h> 2021-02-10 07:22:08 +00:00
ec src/ec/acpi/ec.asl: Convert to ASL 2.0 2021-02-09 07:46:40 +00:00
include device/azalia_device: Add mainboard hook to program codecs 2021-02-10 07:21:11 +00:00
lib coreboot_table: Use precision when printing lb_gpio name 2021-02-10 07:27:38 +00:00
mainboard mb/google/poppy/var/baseboard: Convert to ASL 2.0 2021-02-10 18:01:42 +00:00
northbridge nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors 2021-02-10 07:30:05 +00:00
security security/vboot/bootmode: Add weak fill_lb_gpios 2021-02-09 20:43:12 +00:00
soc soc/amd/cezanne: Add SPI registers 2021-02-10 19:00:34 +00:00
southbridge sb/intel/bd82x6x/acpi: Convert to ASL 2.0 2021-02-10 18:04:48 +00:00
superio
vendorcode vc/amd/fsp/cezanne: add FspGuids.h 2021-02-09 19:13:29 +00:00
Kconfig nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors 2021-02-07 20:20:00 +00:00