coreboot/src
Ionela Voinescu 6b95406ff3 imgtec/pistachio: DDR2, DDR3: DQS gate early
Switching on DQS Gate Early and DQS Gate Extension with
500R DQS/DSQN Resistors. This setup was recommended by
Synopsys.

Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.

Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21 02:05:17 +01:00
..
acpi tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
arch drivers/pc80: Add optional spinlock for nvram CBFS access 2015-12-18 19:47:01 +01:00
commonlib cbfs/vboot: remove firmware component support 2015-12-10 04:43:58 +01:00
console src/console: Add x86 romstage spinlock option and printk spinlock support 2015-12-15 16:41:13 +01:00
cpu drivers/pc80: Add optional spinlock for nvram CBFS access 2015-12-18 19:47:01 +01:00
device x86emu: Remove XFree86 CVS tags 2015-11-20 20:43:54 +01:00
drivers drivers/pc80: Add optional spinlock for nvram CBFS access 2015-12-18 19:47:01 +01:00
ec ec/quanta/ene_kb3940q: Fix ACPI Notice 2015-11-24 22:40:12 +01:00
include lib: Fix strncmp 2015-12-16 01:14:22 +01:00
lib lib: remove assets infrastructure 2015-12-10 04:44:09 +01:00
mainboard mainboard/asus/kgpe-d16: Enable CBFS spinlocks 2015-12-18 19:48:52 +01:00
northbridge southbridge/amd/sr5650: Add MCFG ACPI table support 2015-12-18 19:51:44 +01:00
soc imgtec/pistachio: DDR2, DDR3: DQS gate early 2015-12-21 02:05:17 +01:00
southbridge southbridge/amd/sr5650: Add MCFG ACPI table support 2015-12-18 19:51:44 +01:00
superio superio/smsc/mec1308: Fix IASL warnings 2015-11-24 22:30:19 +01:00
vendorcode vendorcode: google: chromeos: Remove old fmap.c file 2015-12-17 19:55:26 +01:00
Kconfig drivers/pc80: Add optional spinlock for nvram CBFS access 2015-12-18 19:47:01 +01:00