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Kyösti Mälkki 3af6aa10f7 arch/x86: Optimise PCI IO config accessor 
By design only 'reg' parameter can have the two least-
significant bits set. As 'reg' is often a constant,
'0xCFC + (reg & 3)' resolves to an immediate value
already at buildtime, unlike (addr & 3) which depends
of a constant (but non-immediate) value of 'dev' in
ramstage.

Change-Id: I6e729fe800c92b1ce4994ad2b4203072fa75a958
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31754
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14 11:36:09 +00:00
..
acpi
arch arch/x86: Optimise PCI IO config accessor 2019-03-14 11:36:09 +00:00
commonlib commonlib/bubblesort: Do not try to sort less than two entries 2019-03-14 07:48:06 +00:00
console coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
cpu coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
device device/pci_ops: Rename 'where' to 'reg' 2019-03-13 04:42:05 +00:00
drivers drivers/intel/fsp2_0: Add provision to include PPI directory 2019-03-12 04:23:15 +00:00
ec coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
include device/pci_ops: Rename 'where' to 'reg' 2019-03-13 04:42:05 +00:00
lib Remove leftover files 2019-03-14 11:32:06 +00:00
mainboard src/mainboard/pcengines/apu2: Bring back copyrights 2019-03-14 11:34:13 +00:00
northbridge src: Drop unused 'include <arch/ioapic.h>' 2019-03-13 07:29:01 +00:00
security coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
soc soc/intel/cannonlake: Allow mainboard to override DRAM part number 2019-03-13 15:49:05 +00:00
southbridge Remove leftover files 2019-03-14 11:32:06 +00:00
superio Remove leftover files 2019-03-14 11:32:06 +00:00
vendorcode vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for Cometlake 2019-03-12 14:38:31 +00:00
Kconfig Kconfig: Add system type entries for common enclosures 2019-02-05 16:03:29 +00:00