coreboot/arch
Ronald G. Minnich 6a732582c7 Here we start to see the good design of 3. In v2, there were pci ops in
all stages, blighting everything with the same code, compiled different 
ways. In this change, we see that:
- basic conf ops are compiled into stage0, where they are used. 
- they are called directly from initram
- they are used to initialize the pci_cf8_conf1 structure in stage 2, 
   but the call still goes to stage0!

one copy of the code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@752 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-13 02:41:29 +00:00
..
x86 Here we start to see the good design of 3. In v2, there were pci ops in 2008-08-13 02:41:29 +00:00