coreboot/src/soc
Aaron Durbin 588ad7b5db vboot: provide a unified flow for separate verstage
The vboot verification in a stage proper is unified
replacing duplicate code in the tegra SoC code. The
original verstage.c file is renamed to reflect its
real purpose. The support for a single verstage flow
is added to the vboot2 directory proper.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built glados.

Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11744
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30 06:58:02 +00:00
..
broadcom/cygnus linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
imgtec/pistachio linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
intel cpu: microcode: Use microcode stored in binary format 2015-09-30 06:57:19 +00:00
marvell/bg4cd linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
nvidia vboot: provide a unified flow for separate verstage 2015-09-30 06:58:02 +00:00
qualcomm/ipq806x linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
rockchip/rk3288 linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
samsung linking: link bootblock.elf with .data and .bss sections again 2015-09-22 21:22:44 +00:00
ucb/riscv Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00