coreboot/src/soc
Ronak Kanabar 69a9565339 soc/intel/cannonlake: SoC specific microcode update check
For CFL and WHL, Microcode is being loaded from FIT. Both
supports the PRMRR/SGX feature. If This is supported the FIT
microcode load will set the msr (0x08b) with the Patch id one
less than the id in the microcode binary. This results in
Microcode getting reloaded again in bootblock and ramstage.
Avoid the microcode reload by checking for PRMRR support.
CFL and WHL CPU die are based on KBL CPU so we need to have
this check, where CNL CPU die is not based on KBL CPU so
skip this check for CNL.

BUG=b:124126405
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>

Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955
Reviewed-on: https://review.coreboot.org/c/31492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-02-21 19:10:23 +00:00
..
amd ACPI: Correct asl_compiler_revision value 2019-02-21 19:07:31 +00:00
cavium bootmem: add new memory type for BL31 2019-02-05 13:41:45 +00:00
imgtec (console,drivers/uart)/Kconfig: Fix dependencies 2018-11-21 22:49:48 +00:00
intel soc/intel/cannonlake: SoC specific microcode update check 2019-02-21 19:10:23 +00:00
mediatek bootmem: add new memory type for BL31 2019-02-05 13:41:45 +00:00
nvidia bootmem: add new memory type for BL31 2019-02-05 13:41:45 +00:00
qualcomm console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
rockchip bootmem: add new memory type for BL31 2019-02-05 13:41:45 +00:00
samsung src: Don't use a #defines like Kconfig symbols 2019-01-28 13:41:28 +00:00
sifive riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV 2019-01-24 14:21:01 +00:00
ucb riscv: Add initial support for 32bit boards 2019-02-13 04:49:14 +00:00