coreboot/src/ram
Eric W. Biederman 2beb0a1bcc - Updates for the supermicro p4dc6 motherboard
- Code to initialize sdram from C on the l440gx
- cache as ram code fro the p6 it works except conflict misses occur
  with addresses that are not cached so writing to ram does not work.
  Which makes it to brittle to count on.
- Initial implementation of a fallback booting scheme where we can
  have two copies of linuxbios in rom at once.
- Movement of 32 bit entry code from entry16.inc to entry32.inc
- Update of all config files so they now also include entry32.inc
- Fix for start_stop.c & entry16.inc so I can fairly arbitrarily relocate
  the 16bit entry code in SMP.
- A small number of fixes for warnings
2001-11-27 19:29:59 +00:00
..
Config - Updates for the supermicro p4dc6 motherboard 2001-11-27 19:29:59 +00:00
ramtest.c - Updates for the supermicro p4dc6 motherboard 2001-11-27 19:29:59 +00:00
ramtest.inc - Delayed commit of code for the ASUS A7M motherboard 2001-11-13 03:43:37 +00:00