Arthur Heymans 695dd2977b soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR ... This makes coreboot more robust as it does not need to rely on syncing values set by FSP and coreboot. Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47533 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-11-20 10:17:56 +00:00
..
alderlake	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	2020-11-20 00:12:09 +00:00
apollolake	soc/intel/apollolake: use P2SB function to generate DMAR HPET	2020-11-20 10:17:33 +00:00
baytrail	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
braswell	src: Update some incorrect config options in comments	2020-11-16 12:09:58 +00:00
broadwell	soc/intel/broadwell/systemagent.c: Rename to northbridge.c	2020-11-16 11:06:30 +00:00
cannonlake	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	2020-11-20 00:12:09 +00:00
common	soc/intel/common/block/p2sb: Add hpet BDF functions	2020-11-20 10:17:22 +00:00
denverton_ns	soc/intel/denverton_ns: Initialize thermal configuration	2020-11-20 00:43:10 +00:00
elkhartlake	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	2020-11-20 00:12:09 +00:00
icelake	soc/intel/*/chip: Remove unused devicetree entry	2020-11-09 07:27:38 +00:00
jasperlake	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	2020-11-20 00:12:09 +00:00
quark	arch/x86: Introduce ARCH_ALL_STAGES_X86_32	2020-09-26 11:42:28 +00:00
skylake	soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig	2020-11-13 17:32:37 +00:00
tigerlake	soc/intel/tigerlake: Enable GPIO IOSTANDBY configuration	2020-11-20 00:25:37 +00:00
xeon_sp	soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR	2020-11-20 10:17:56 +00:00
Kconfig