coreboot/src
Vadim Bendebury 690ac93aa0 rk3399: allow more room for CBMEM console
With recent bootblock code additions the CBMEM console buffer is not
large enough to store the entire log accumulated before DRAM is
initialized, spilling 700 bytes or so on the floor.

This patch adds 1 KB to the CBMEM console buffer, at the expense of the
bootblock area in SRAM. The bootblock is taking less then 26K out of
31K allocated for it after this change.

Placing CBMEM console area right after the bootblock makes sure other
memory regions are not going to be affected should memory distribution
between bootblock and CBMEM console need to change again.

BRANCH=none
BUG=none
TEST=examining /sys/firmware/log after device boots up into Chrome OS
     does not report truncated console buffer any more.

Change-Id: I016460f57c70dab4d603d4c5dbfc5ffbc6c3554f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: bfa31684a1
Original-Change-Id: I2c3d198803e6f083ddd1d8447aa377ebf85484ce
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/358125
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15607
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13 23:57:33 +02:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch acpi: Change device properties to work as a tree 2016-07-08 17:21:26 +02:00
commonlib region: Add writeat and eraseat support 2016-06-24 20:48:12 +02:00
console console/post: be explicit about conditional cmos_post_log() compiling 2016-05-25 18:04:11 +02:00
cpu intel post-car: Consolidate choose_top_of_stack() 2016-07-10 11:16:07 +02:00
device device: i2c: Add support for I2C bus operations 2016-06-09 17:05:40 +02:00
drivers tpm: report firmware version 2016-07-12 00:26:42 +02:00
ec google/chromeec: Update EC command header 2016-07-10 03:54:07 +02:00
include SPD: Add CAS latency 2 2016-07-12 15:17:31 +02:00
lib lib/selfboot: clear BSS segments 2016-07-12 23:39:14 +02:00
mainboard gru: Enable TPM2 2016-07-13 23:57:08 +02:00
northbridge nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM 2016-07-09 13:49:00 +02:00
soc rk3399: allow more room for CBMEM console 2016-07-13 23:57:33 +02:00
southbridge Documentation: Fix doxygen errors 2016-07-12 22:41:02 +02:00
superio sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-29 19:34:54 +02:00
vendorcode vboot2: tpm2 factory initialization. 2016-07-12 00:27:27 +02:00
Kconfig Romstage spinlocks require EARLY_CBMEM_INIT 2016-07-10 04:03:31 +02:00