Kyösti Mälkki 6766f4fd04 arch/x86: Fix S3 resume without stage cache ... It was possible to have NO_STAGE_CACHE=n and at the same time have TSEG_STAGE_CACHE=n and CBMEM_STAGE_CACHE=n. This resulted with a failing attempt to load STAGE_POSTCAR from the stage cache, but not loading it from CBFS either. Make it a three-way choice between different STAGE_CACHE options. For AGESA disable CBMEM_STAGE_CACHE by default, as it is no longer needed to have functional ACPI S3 resume and it is not allowed se use keyword select for symbols inside choice blocks. Change-Id: I0da3e1cf4c92817ffabbb02eda3476ecdfdfa278 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37683 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-12-19 19:30:40 +00:00
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amd	arch/x86: Fix S3 resume without stage cache	2019-12-19 19:30:40 +00:00
armltd	Kconfig: comply to Linux 5.3's Kconfig language rules	2019-11-23 20:09:56 +00:00
intel	src: Remove unused 'include <arch/cpu.h>'	2019-12-19 05:58:50 +00:00
qemu-power8	AUTHORS: Move src/cpu copyrights into AUTHORS file	2019-09-10 12:51:22 +00:00
qemu-x86	Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol	2019-11-25 09:17:38 +00:00
ti	fmap: Make FMAP_CACHE mandatory if it is configured in	2019-12-11 11:42:26 +00:00
x86	src: Remove unused 'include <arch/cpu.h>'	2019-12-19 05:58:50 +00:00
Kconfig	kill CAR_GLOBAL_MIGRATION leftovers	2019-11-30 16:12:04 +00:00
Makefile.inc	soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T	2019-11-26 11:55:10 +00:00