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Mario Scheithauer 65ca24c02e siemens/mc_apl4: Change UART_FOR_CONSOLE index 
This mainboard uses SOC internal UART 1 instead of UART 2 like all other
mc_apl1 mainboards.

Change-Id: Ib986962ed068fee019ffcec0391d43d5ab178458
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-16 07:13:39 +00:00
..
acpi
arch arch/x86: Enforce CPU stack alignment 2019-01-14 11:59:51 +00:00
commonlib src: Remove duplicated round up function 2018-11-29 12:17:45 +00:00
console console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
cpu cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup 2019-01-15 11:38:01 +00:00
device device/pci_device: Do not break tree topology 2019-01-10 12:47:18 +00:00
drivers drivers/spi/stmicro.c: Add the rest of >=1MB STMicro M25/N25 chips 2019-01-16 00:21:24 +00:00
ec ec/chromeec: fix LPC read/write for MEC devices 2018-12-28 12:24:52 +00:00
include cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK 2019-01-08 15:33:47 +00:00
lib src: Get rid of device_t 2019-01-04 12:11:18 +00:00
mainboard siemens/mc_apl4: Change UART_FOR_CONSOLE index 2019-01-16 07:13:39 +00:00
northbridge AGESA: Drop CONFIG_CBB and CONFIG_CDB 2019-01-14 19:08:34 +00:00
security tss: implement tlcl_save_state 2018-11-28 18:32:59 +00:00
soc soc/intel/apl: Hook microcode updates up 2019-01-15 09:19:11 +00:00
southbridge AGESA: Drop CONFIG_CBB and CONFIG_CDB 2019-01-14 19:08:34 +00:00
superio src/superio/smsc/smscsuperio/superio.c: Add SCH5504 2019-01-15 09:35:31 +00:00
vendorcode vendorcode/intel/fsp1_0/broadwell_de: Use FSP from 3rdparty/fsp 2019-01-15 07:45:41 +00:00
Kconfig [RFC]util/checklist: Remove this functionality 2019-01-14 19:42:59 +00:00