John Zhao 64fb5aa9c3 soc/intel/common: Set GSPI clock value to prevent division by zero ... Clang Static Analyzer version 8.0.0 detects the division by zero if gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to prevent the division by zero in DIV_ROUND_UP operation. Then the value of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value. TEST=Built and boot up to kernel. Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>		2019-05-29 20:07:26 +00:00
..
apollolake	soc/intel/apollolake: Don't use CAR_GLOBAL	2019-05-29 20:02:57 +00:00
baytrail	soc/{baytrail/braswell/broadwell}: fix flashconsole on platform	2019-05-22 10:06:50 +00:00
braswell	soc/intel/braswell: Don't use CAR_GLOBAL	2019-05-29 20:03:28 +00:00
broadwell	Clean up unused arch/early_variables.h header	2019-05-29 20:03:14 +00:00
cannonlake	soc/intel/cannonlake: Dump ME status info before notify EndOfFirmware	2019-05-28 20:13:59 +00:00
common	soc/intel/common: Set GSPI clock value to prevent division by zero	2019-05-29 20:07:26 +00:00
denverton_ns	soc/intel/denverton_ns: Remove variable set but not used	2019-05-23 08:54:02 +00:00
fsp_baytrail	soc/intel/fsp_baytrail/romstage: Remove variable set but not used	2019-05-23 08:58:33 +00:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de/romstage: Remove variable set but not used	2019-05-23 08:58:15 +00:00
icelake	post_code: add post code for hardware initialization failure	2019-05-22 17:44:53 +00:00
quark	soc/intel/quark: Don't use CAR_GLOBAL	2019-05-29 20:05:06 +00:00
skylake	Clean up unused arch/early_variables.h header	2019-05-29 20:03:14 +00:00
Kconfig	src/cpu: Remove dead sourced lines	2018-11-15 10:25:20 +00:00