Jonathan Zhang 7919d618f8 soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration ... Add PCIe enumeration and resource assignment/allocation. Xeon-SP processor family has split IIO design, where PCIe domain 0 is split into multiple stacks. Each stack has its own resource ranges (eg. IO resource, mem32 resource, mem64 resource). The stack itself is not PCIe device, it does not have config space to be probed/programmed. The stack is programmed by FSP. coreboot needs to take into account of stack when doing PCIe enumeration and resource allocation. Current coreboot PCIe resource allocator does not support the concept of split IIO stack, thus entire support is done locally in this patch. In near future, improvements will be done, first generalize for xeon-sp, then generalize for coreboot PCIe device code. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>		2020-06-04 15:42:10 +00:00
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amd	soc/amd/picasso: fix iomap for ACPI_PM	2020-06-04 15:02:29 +00:00
cavium	src: Remove redundant includes	2020-06-02 07:42:32 +00:00
intel	soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration	2020-06-04 15:42:10 +00:00
mediatek	src: Remove redundant includes	2020-06-02 07:42:32 +00:00
nvidia	src: Remove redundant includes	2020-06-02 07:42:32 +00:00
qualcomm	src: Remove unused '#include <timer.h>'	2020-06-02 07:39:05 +00:00
rockchip	src: Remove leading blank lines from SPDX header	2020-05-18 07:00:27 +00:00
samsung	samsung/exynos5420: add resources during read_resources()	2020-05-14 21:27:34 +00:00
sifive	soc/sifive/fu540: Add chip_operations stub	2020-05-28 09:30:51 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00