Andrey Petrov 6401188024 soc/intel/common: Add reset_prepare() for common reset ... Some Intel SoC may need preparation before reset can be properly handled. Add callback that chip/soc code can implement. BUG=chrome-os-partner:55055 Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-07-19 20:20:13 +02:00
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acpi	arch/x86: provide common Intel ACPI hardware definitions	2016-07-15 08:31:21 +02:00
arch	arch/riscv: Remove enter_supervisor	2016-07-18 22:51:13 +02:00
commonlib	drivers/intel/fsp2_0: load and relocate FSPS in cbmem	2016-07-19 20:18:08 +02:00
console	console/post: be explicit about conditional cmos_post_log() compiling	2016-05-25 18:04:11 +02:00
cpu	AMD binaryPI: Use common romstage ram stack	2016-07-15 12:31:07 +02:00
device	device: i2c: Add support for I2C bus operations	2016-06-09 17:05:40 +02:00
drivers	drivers/intel/fsp2_0: handle reset requests from FSPS	2016-07-19 20:19:25 +02:00
ec	ec/google/chromeec: provide common SMI handler helpers	2016-07-15 08:35:29 +02:00
include	soc/intel/common: Add reset_prepare() for common reset	2016-07-19 20:20:13 +02:00
lib	lib: provide memrange library in romstage	2016-07-19 20:13:20 +02:00
mainboard	mainboard/google/reef: explicitly set shipping Chrome OS options	2016-07-19 20:13:08 +02:00
northbridge	nb/intel/x4x: Fix CAS latency detection	2016-07-19 18:55:50 +02:00
soc	soc/intel/common: Add reset_prepare() for common reset	2016-07-19 20:20:13 +02:00
southbridge	southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitions	2016-07-15 08:34:46 +02:00
superio	sio/winbond/w83667hg-a: Add pinmux defines for UART B	2016-05-29 19:34:54 +02:00
vendorcode	chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sections	2016-07-15 00:40:19 +02:00
Kconfig	Romstage spinlocks require EARLY_CBMEM_INIT	2016-07-10 04:03:31 +02:00