Tim Wawrzynczak b6a15a7227 soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs ... The PMC IPC method that is used for RTD3 support expects to be provided the virtual wire index instead of the LCAP PN for CPU PCIe RPs. Therefore, use the prior patches to update pcie_rp for CPU RPs. Note that an unused argument to pcie_rtd3_acpi_method_status() was also dropped. BUG=b:197983574 TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and inspect the SSDT to see the PMC IPC parameters are as expected for the CPU RP, and the ModPhy power gating code is not found in the AML for the PEG port. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Crawford <tcrawford@system76.com> Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60183 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-01-07 20:00:09 +00:00
..
acpi	soc/intel: generate SSDT instead of using GNVS for SGX	2021-11-09 16:02:19 +00:00
basecode
block	soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs	2022-01-07 20:00:09 +00:00
pch	soc/intel/common/pch: Fix return value documentation for CHIPSET_LOCKDOWN	2021-12-08 22:29:52 +00:00
fsp_reset.c
hda_verb.c
hda_verb.h
Kconfig.common	soc/intel/common: Do not trigger crashlog on all resets by default	2021-12-20 17:49:53 +00:00
Makefile.inc	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
mma.c
mma.h
nhlt.c
reset.c
reset.h
smbios.c	arch/x86: Refactor the SMBIOS type 17 write function	2021-11-11 09:10:10 +00:00
smbios.h
tpm_tis.c
vbt.c
vbt.h