coreboot/src
Antonello Dettori 6321d7c14b roda/rk9: Remove #include early_serial.c from romstage
Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Also re-organize some of the superio code in order
to succesfully compile the rom.

Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08 13:41:03 +01:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch arch/x86: Add common assembly code for stages that run in CAR 2016-03-05 20:11:35 +01:00
commonlib lz4_wrapper: Use __asm__ rather than asm. 2016-03-05 00:56:53 +01:00
console Kconfig: hide useless options on ARM. 2016-03-05 00:56:36 +01:00
cpu arch/x86: document CAR symbols and expose them in symbols.h 2016-03-05 16:00:42 +01:00
device Kconfig: hide useless options on ARM. 2016-03-05 00:56:36 +01:00
drivers tpm/acpi/tpm.asl: Only include tpm.asl if tpm is enabled 2016-03-05 22:51:03 +01:00
ec Hide EC_GOOGLE_CHROMEEC_SPI_BUS. 2016-03-05 00:57:22 +01:00
include include/device/dram: Fix DDR3-1866 2016-03-05 15:35:14 +01:00
lib lib/bootblock: provide SoC callback parity with mainboard 2016-02-26 02:16:14 +01:00
mainboard roda/rk9: Remove #include early_serial.c from romstage 2016-03-08 13:41:03 +01:00
northbridge sandybridge/gma_lvds: support both Sandy&Ivy on one board 2016-03-05 09:39:41 +01:00
soc intel/fsp_baytrail: use 20K PU/PD for GPIO 2016-03-07 04:24:57 +01:00
southbridge southbridge/intel/ibexpeak: Use common gpio.c 2016-02-23 00:28:26 +01:00
superio roda/rk9: Remove #include early_serial.c from romstage 2016-03-08 13:41:03 +01:00
vendorcode vboot: Set S3_RESUME flag for vboot context if necessary 2016-02-29 20:18:33 +01:00
Kconfig cbfs: Add LZ4 in-place decompression support for pre-RAM stages 2016-02-22 21:38:37 +01:00