Felix Held 62afdb675a soc/amd/cezanne: factor out eSPI SPI2 pads configuration functions ... verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses some of the registers directly. BUG=b:183149183 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2022-01-14 00:29:52 +00:00
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cezanne	soc/amd/cezanne: factor out eSPI SPI2 pads configuration functions	2022-01-14 00:29:52 +00:00
common	soc/amd/common/block: add new PCI IDs to common code	2022-01-12 00:44:50 +00:00
picasso	soc/amd/*/chip.h: add missing gpio.h include	2022-01-13 18:08:14 +00:00
stoneyridge	soc/amd/*/chip.h: add missing gpio.h include	2022-01-13 18:08:14 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00