Furquan Shaikh d36ed272b2 soc/intel/apollolake: Implement SPI flash status register read ... This was a dummy implementation until now which returned -1 always. Add support for reading SPI flash status register (srp0). BUG=chrome-os-partner:59267 BRANCH=None TEST=Verified by enabling and disabling write-protect on reef that the value of SRP0 changes accordingly in status register read. Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17205 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-11-03 05:36:03 +01:00
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apollolake	soc/intel/apollolake: Implement SPI flash status register read	2016-11-03 05:36:03 +01:00
baytrail	lib/prog_loaders: use common ramstage_cache_invalid()	2016-10-31 19:34:20 +01:00
braswell	Makefile.inc: Use $(MAINBOARDDIR)	2016-09-04 05:33:25 +02:00
broadwell	lib/prog_loaders: use common ramstage_cache_invalid()	2016-10-31 19:34:20 +01:00
common	soc/intel/common: Add reset.c to postcar	2016-10-29 00:23:09 +02:00
fsp_baytrail	fsp_baytrail: Refactor code for SPI debug messages	2016-09-06 21:17:59 +02:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled	2016-10-09 19:08:07 +02:00
quark	soc/intel/quark: Fix FSP 2.0 build	2016-09-30 01:16:51 +02:00
sch	src/soc: Remove unnecessary whitespace before "\n" and "\t"	2016-08-28 18:25:14 +02:00
skylake	intel/{skylake,apollolake}: Enable signalling of error condition	2016-11-02 17:29:37 +01:00