ca584085d7
Add Type-C subsystem power management support for RTD3. BUG=b:140290596 TEST=Include "tcss.asl" in platform "dsdt.asl" for coreboot build with the firmware CM. Added acpi debug and booted to kernel. Probed devices PM_STATE transition from D0 to D3 entry/exit while system at S0. TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3, offset:0xA4, PM_STATE:D3HT. xhci:00:0d.0, offset:0x74, PM_STATE:D0D3. dma:00:0d.2/00.0d.3, offset:0x84, PM_STATE:PMST. Verified xhci/dma/pcie root ports power runtime_status to be suspended and suspended time tick through /sys/bus/pci/devices/bus:device:func/power. Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> |
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