coreboot/src
David Hendricks 5f6ffbab1b exynos5420: add CPLL and DPLL to the known list of PLLs
This patch adds CPLL and DPLL to the known list of PLLs.

This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af
Reviewed-on: https://gerrit.chromium.org/gerrit/65282
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4461
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:28 +01:00
..
arch exynos5250: Implement support to boot with USB A-A firmware upload 2013-12-21 22:46:15 +01:00
console snprintf: lockless operation 2013-12-07 19:27:53 +01:00
cpu exynos5420: add CPLL and DPLL to the known list of PLLs 2013-12-21 22:46:28 +01:00
device Add Kconfig options to override Subsystem Vendor and Device ID 2013-12-21 12:02:40 +01:00
drivers max77802: update header 2013-12-21 13:29:42 +01:00
ec chromeec: Add event methods for EC requested throttle 2013-12-21 12:02:14 +01:00
include Add a specific post code for S3 resume failures 2013-12-21 12:02:43 +01:00
lib Pit: graphics 2013-12-21 22:45:06 +01:00
mainboard exynos5420: Configure the UART pins unconditionally 2013-12-21 22:46:20 +01:00
northbridge haswell: add option to change DqPinsInterleaved 2013-12-21 12:02:56 +01:00
southbridge lynxpoint: Add configuration option for SATA gen3 DTLE registers 2013-12-21 12:03:00 +01:00
superio Correct file permissions. 2013-12-07 00:39:09 +01:00
vendorcode chromeos: Check for recovery reason code in shared data 2013-12-21 07:28:37 +01:00
Kconfig Add GRUB2 payload to build system 2013-11-19 01:07:25 +01:00