1732dcb90c
In some cases it may be useful to be able to bitbang a UART, such as during early bring-up when a driver for the actual controller isn't available yet. On some platforms we may even want to use this permanently, such as on the SDM845 where the hardware UART controller needs to have firmware loaded and is thus unavailable for most of the bootblock. This patch adds some helper code that makes it easy to implement this on a platform, you just have to pass it a function to control the Tx pin state and it will do the rest. It relies on the mono_time API and is thus bound to microsecond timing granularity, but that seems to be barely good enough for 115200 baud if the bit times are calculated carefully. Change-Id: If7dcecc7b8a95ec15f456efd2ec1f1e0dde239b4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25812 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
84 lines
2.7 KiB
C
84 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <console/uart.h>
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#include <types.h>
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#include <timer.h>
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/* Calculate divisor. Do not floor but round to nearest integer. */
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unsigned int uart_baudrate_divisor(unsigned int baudrate,
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unsigned int refclk, unsigned int oversample)
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{
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return (1 + (2 * refclk) / (baudrate * oversample)) / 2;
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}
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#if !IS_ENABLED(CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER)
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unsigned int uart_input_clock_divider(void)
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{
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/* Specify the default oversample rate for the UART.
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*
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* UARTs oversample the receive data. The UART's input clock first
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* enters the baud-rate divider to generate the oversample clock. Then
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* the UART typically divides the result by 16. The asynchronous
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* receive data is synchronized with the oversample clock and when a
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* start bit is detected the UART delays half a bit time using the
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* oversample clock. Samples are then taken to verify the start bit and
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* if present, samples are taken for the rest of the frame.
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*/
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return 16;
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}
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#endif
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#if !IS_ENABLED(CONFIG_UART_OVERRIDE_REFCLK)
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unsigned int uart_platform_refclk(void)
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{
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/* Specify the default input clock frequency for the UART.
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*
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* The older UART's used an input clock frequency of 1.8432 MHz which
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* with the 16x oversampling provided the maximum baud-rate of 115200.
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* Specify this as maximum baud-rate multiplied by oversample so that
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* it is obvious that the maximum baud rate is 115200 when divided by
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* oversample clock. Also note that crystal on the board does not
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* change when software selects another input clock divider.
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*/
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return 115200 * 16;
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}
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#endif
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/* Helper function to allow bitbanging an 8n1 UART. */
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void uart_bitbang_tx_byte(unsigned char data, void (*set_tx)(int line_state))
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{
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const int baud_rate = get_uart_baudrate();
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int i;
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struct stopwatch sw;
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stopwatch_init(&sw);
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/* Send start bit */
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set_tx(0);
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while (stopwatch_duration_usecs(&sw) < MHz / baud_rate)
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stopwatch_tick(&sw);
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/* 'i' counts the total bits sent at the end of the loop */
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for (i = 2; i < 10; i++) {
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set_tx(data & 1);
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data >>= 1;
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while (stopwatch_duration_usecs(&sw) < i * MHz / baud_rate)
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stopwatch_tick(&sw);
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}
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/* Send stop bit */
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set_tx(1);
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while (stopwatch_duration_usecs(&sw) < i * MHz / baud_rate)
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stopwatch_tick(&sw);
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}
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