5d3f4d0fcb
Have the Skylake SOC generate ACPI timing values for the enabled I2C controllers instead of passing it in the DSDT with static timings. The timing values are generated from the controller clock speed and are more accurate than the hardcoded values that were in the ASL which were originally copied from Broadwell where the controller is running at a different clock speed... Additionally it is now possible for a board to override the values using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then the kernel will generate its own timing using the same forumla, but if the SDA hold time value is zero the kernel will NOT generate a correct value and the SDA hold time may be incorrect. This was tested on the Chell platform to ensure all the I2C devices on the board are still operational with these new timing values. BUG=None BRANCH=None TEST=None Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://review.coreboot.org/15291 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/358386 Reviewed-by: Martin Roth <martinroth@chromium.org> |
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| broadcom/cygnus | ||
| dmp/vortex86ex | ||
| imgtec/pistachio | ||
| intel | ||
| marvell | ||
| mediatek/mt8173 | ||
| nvidia | ||
| qualcomm | ||
| rdc/r8610 | ||
| rockchip | ||
| samsung | ||
| ucb/riscv | ||