coreboot/src
Lee Leahy 6c8701245c UPSTREAM: soc/intel/quark: Set CBMEM top from HW register
Properly obtain the top of memory address from the hardware registers
set by FSP.

TEST=Build and run on Galileo Gen2

Change-Id: I7681d32112408b8358b4dad67f8d69581c7dde2e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15594
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360200
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12 22:34:29 -07:00
..
acpi
arch UPSTREAM: acpi: Change device properties to work as a tree 2016-07-09 01:39:55 -07:00
commonlib UPSTREAM: lib: Add real-time-clock functions 2016-07-07 01:08:44 -07:00
console
cpu UPSTREAM: intel post-car: Consolidate choose_top_of_stack() 2016-07-11 21:27:25 -07:00
device UPSTREAM: device: i2c: Add support for I2C bus operations 2016-06-10 00:17:46 -07:00
drivers UPSTREAM: intel post-car: Consolidate choose_top_of_stack() 2016-07-11 21:27:25 -07:00
ec google/chromeec: Update EC command header 2016-06-23 15:15:09 -07:00
include UPSTREAM: SPD: Add CAS latency 2 2016-07-12 22:34:24 -07:00
lib UPSTREAM: intel post-car: Consolidate choose_top_of_stack() 2016-07-11 21:27:25 -07:00
mainboard Increase RO coreboot size on flash 2016-07-11 10:23:07 -07:00
northbridge UPSTREAM: nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM 2016-07-11 21:27:15 -07:00
soc UPSTREAM: soc/intel/quark: Set CBMEM top from HW register 2016-07-12 22:34:29 -07:00
southbridge UPSTREAM: PCI: Use PCI_DEVFN macro instead of DEV_FUNC 2016-07-07 01:09:48 -07:00
superio
vendorcode UPSTREAM: soc/intel/quark: Pass in the memory initialization parameters 2016-07-09 01:40:13 -07:00
Kconfig UPSTREAM: Romstage spinlocks require EARLY_CBMEM_INIT 2016-07-11 21:27:20 -07:00